// **************************************************************
// COPYRIGHT(c)2016, Xidian University
// All rights reserved.
//
// IP LIB INDEX :  
// IP Name      :      
// File name    :  
// Module name  :  
// Full name    :  
// Time         : 2016 
// Author       : Wang-Weina 
// Email        : 327422289@qq.com
// Data         : 
// Version      : V 1.0 
// 
// Abstract     :
// Called by    :  
// 
// Modification history
// -----------------------------------------------------------------
// 
// 
//
// *****************************************************************
`include "top_define.v"
// *******************
// TIMESCALE
// ******************* 
`timescale 1ns/1ps 

// *******************
// INFORMATION
// *******************

//*******************
//DEFINE(s)
//*******************
//`define UDLY 1    //Unit delay, for non-blocking assignments in sequential logic

//*******************
//DEFINE MODULE PORT
//*******************
module rbve_2(
    input wire clk,
    input wire rst_n,
    input wire [11:0]ram_dp_cfg_register,
    input wire[7:0] range_second,
    input wire lookup_en,
    input wire[ 7:0] addr_loc,
    input wire[63:0] cpu_data,
    output reg[63:0] cpu_data_o_ff,
    input wire mod_en,
    output reg[1:0] rbve_out_r0 ,
    output reg[1:0] rbve_out_r1 ,
    output reg[1:0] rbve_out_r2 ,
    output reg[1:0] rbve_out_r3 ,
    output reg[1:0] rbve_out_r4 ,
    output reg[1:0] rbve_out_r5 ,
    output reg[1:0] rbve_out_r6 ,
    output reg[1:0] rbve_out_r7 ,
    output reg[1:0] rbve_out_r8 ,
    output reg[1:0] rbve_out_r9 ,
    output reg[1:0] rbve_out_r10,
    output reg[1:0] rbve_out_r11,
    output reg[1:0] rbve_out_r12,
    output reg[1:0] rbve_out_r13,
    output reg[1:0] rbve_out_r14,
    output reg[1:0] rbve_out_r15,
    output reg[1:0] rbve_out_r16,
    output reg[1:0] rbve_out_r17,
    output reg[1:0] rbve_out_r18,
    output reg[1:0] rbve_out_r19,
    output reg[1:0] rbve_out_r20,
    output reg[1:0] rbve_out_r21,
    output reg[1:0] rbve_out_r22,
    output reg[1:0] rbve_out_r23,
    output reg[1:0] rbve_out_r24,
    output reg[1:0] rbve_out_r25,
    output reg[1:0] rbve_out_r26,
    output reg[1:0] rbve_out_r27,
    output reg[1:0] rbve_out_r28,
    output reg[1:0] rbve_out_r29,
    output reg[1:0] rbve_out_r30,
    output reg[1:0] rbve_out_r31

);

//*******************
//DEFINE LOCAL PARAMETER
//*******************
//parameter(s)

//*********************
//INNER SIGNAL DECLARATION
//*********************
//REGS
    
reg[7:0] addra;
reg lookup_en_ff1,lookup_en_ff2;
//WIRES
wire[63:0] douta;
wire[63:0] cpu_data_o;

reg [63:0] douta_ff;
//*********************
//INSTANTCE MODULE
//*********************
`ifdef ASIC //2021/8/28
reg cena,cenb;
ram_dp_d256_w64_wrapper U1_asic(
    .clka(clk),
    .clkb(clk),
    .ram_dp_cfg_register(ram_dp_cfg_register),
    .wea(1'b0),
    .addra(addra),
    .dina(64'b0),
    .douta(douta), //\u8bfb

    .cena(cena),
    .cenb(cenb),

    .web(mod_en),
    .addrb(addr_loc),
    .dinb(cpu_data),
    .doutb(cpu_data_o)
);
always@(*)begin
    if(mod_en && (addra == 0))begin
        cena = 1'b1;
        cenb = 1'b0;
    end
    else begin
        cena = 1'b0;
        cenb = 1'b0;
    end
end

`else
//FPGA
bram_18K U1(
    .clka(clk),
    .rst_n(rst_n),
    .addra(addra),
    .douta(douta),
    .wr_en(mod_en),
    .addrb(addr_loc),
    .dinb(cpu_data),
    .doutb(cpu_data_o)
    );
`endif
// //ASIC
// bram_18K U1(
//     .clka (clk       ),
//     .clkb (clk       ),
// //\u67e5\u627e\u8bbf\u95ee   
//     .wea  (1'b0      ),
//     .addra(addra     ),
//     .dina (64'b0     ),
//     .douta(douta     ),
// //cpu\u914d\u7f6e\u8bfb\u53d6\u8bbf\u95ee\u63a5\u53e3   
//     .web  (mod_en    ),
//     .addrb(addr_loc  ),
//     .dinb (cpu_data  ),
//     .doutb(cpu_data_o)  
//     );
 

//*********************
//MAIN CORE
//********************* 

always@(*)
  begin
    if(~rst_n)
      addra = 8'b0;
    else if(lookup_en)
      begin
          addra = range_second;
      end
    else 
      begin
          addra = 8'b0;
      end
  end

always@(posedge clk or negedge rst_n)
  begin
    if(~rst_n)begin
      lookup_en_ff1 <= 0;
      lookup_en_ff2 <= 0;
    end
    else begin
      lookup_en_ff1 <= lookup_en;
      lookup_en_ff2 <= lookup_en_ff1;
    end
  end

always@(posedge clk or negedge rst_n)
  begin
    if(~rst_n)begin
      douta_ff      <= 0;
      cpu_data_o_ff <= 0;
    end
    else begin
      douta_ff      <= douta;
      cpu_data_o_ff <= cpu_data_o;
    end
  end

always@(posedge clk or negedge rst_n)
  begin
    if(~rst_n)
      begin
        rbve_out_r0   <=2'b0;
        rbve_out_r1   <=2'b0;
        rbve_out_r2   <=2'b0;
        rbve_out_r3   <=2'b0;
        rbve_out_r4   <=2'b0;
        rbve_out_r5   <=2'b0;
        rbve_out_r6   <=2'b0;
        rbve_out_r7   <=2'b0;
        rbve_out_r8   <=2'b0;
        rbve_out_r9   <=2'b0;
        rbve_out_r10  <=2'b0;
        rbve_out_r11  <=2'b0;
        rbve_out_r12  <=2'b0;
        rbve_out_r13  <=2'b0;
        rbve_out_r14  <=2'b0;
        rbve_out_r15  <=2'b0;
        rbve_out_r16  <=2'b0;
        rbve_out_r17  <=2'b0;
        rbve_out_r18  <=2'b0;
        rbve_out_r19  <=2'b0;
        rbve_out_r20  <=2'b0;
        rbve_out_r21  <=2'b0;
        rbve_out_r22  <=2'b0;
        rbve_out_r23  <=2'b0;
        rbve_out_r24  <=2'b0;
        rbve_out_r25  <=2'b0;
        rbve_out_r26  <=2'b0;
        rbve_out_r27  <=2'b0;
        rbve_out_r28  <=2'b0;
        rbve_out_r29  <=2'b0;
        rbve_out_r30  <=2'b0;
        rbve_out_r31  <=2'b0;
      end
    else if(lookup_en_ff2)
      begin
        rbve_out_r0   <=douta_ff[63:62];
        rbve_out_r1   <=douta_ff[61:60];
        rbve_out_r2   <=douta_ff[59:58];
        rbve_out_r3   <=douta_ff[57:56];
        rbve_out_r4   <=douta_ff[55:54];
        rbve_out_r5   <=douta_ff[53:52];
        rbve_out_r6   <=douta_ff[51:50];
        rbve_out_r7   <=douta_ff[49:48];
        rbve_out_r8   <=douta_ff[47:46];
        rbve_out_r9   <=douta_ff[45:44];
        rbve_out_r10  <=douta_ff[43:42];
        rbve_out_r11  <=douta_ff[41:40];
        rbve_out_r12  <=douta_ff[39:38];
        rbve_out_r13  <=douta_ff[37:36];
        rbve_out_r14  <=douta_ff[35:34];
        rbve_out_r15  <=douta_ff[33:32];
        rbve_out_r16  <=douta_ff[31:30];
        rbve_out_r17  <=douta_ff[29:28];
        rbve_out_r18  <=douta_ff[27:26];
        rbve_out_r19  <=douta_ff[25:24];
        rbve_out_r20  <=douta_ff[23:22];
        rbve_out_r21  <=douta_ff[21:20];
        rbve_out_r22  <=douta_ff[19:18];
        rbve_out_r23  <=douta_ff[17:16];
        rbve_out_r24  <=douta_ff[15:14];
        rbve_out_r25  <=douta_ff[13:12];
        rbve_out_r26  <=douta_ff[11:10];
        rbve_out_r27  <=douta_ff[ 9: 8];
        rbve_out_r28  <=douta_ff[ 7: 6];
        rbve_out_r29  <=douta_ff[ 5: 4];
        rbve_out_r30  <=douta_ff[ 3: 2];
        rbve_out_r31  <=douta_ff[ 1: 0];
      end
    else 
      begin
        rbve_out_r0   <=2'b0;
        rbve_out_r1   <=2'b0;
        rbve_out_r2   <=2'b0;
        rbve_out_r3   <=2'b0;
        rbve_out_r4   <=2'b0;
        rbve_out_r5   <=2'b0;
        rbve_out_r6   <=2'b0;
        rbve_out_r7   <=2'b0;
        rbve_out_r8   <=2'b0;
        rbve_out_r9   <=2'b0;
        rbve_out_r10  <=2'b0;
        rbve_out_r11  <=2'b0;
        rbve_out_r12  <=2'b0;
        rbve_out_r13  <=2'b0;
        rbve_out_r14  <=2'b0;
        rbve_out_r15  <=2'b0;
        rbve_out_r16  <=2'b0;
        rbve_out_r17  <=2'b0;
        rbve_out_r18  <=2'b0;
        rbve_out_r19  <=2'b0;
        rbve_out_r20  <=2'b0;
        rbve_out_r21  <=2'b0;
        rbve_out_r22  <=2'b0;
        rbve_out_r23  <=2'b0;
        rbve_out_r24  <=2'b0;
        rbve_out_r25  <=2'b0;
        rbve_out_r26  <=2'b0;
        rbve_out_r27  <=2'b0;
        rbve_out_r28  <=2'b0;
        rbve_out_r29  <=2'b0;
        rbve_out_r30  <=2'b0;
        rbve_out_r31  <=2'b0;
      end
  end
//*********************
endmodule    // hookup byte controller block
